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Professors: Luca Di Nunzio, Sergio Spanò, Vittorio Melini
E-mail: {di.nunzio,spano}@ing.uniroma2.it
Course Program:
(L. DI NUNZIO)
Digital electronics basic concepts
Floating point and fixed-point numeric representation formats
Combinatorial circuits: encoders, decoders, multiplexers
Sequential circuits: flip flops, latch registers, counters, memories
Introduction to VHDL: entity and architecture, levels of abstraction, HDL design flow, combinatorial and sequential processes, objects in VHDL test bench
Practical activities of circuit design in VHDL
(S. SPANÒ)
Central unit
ALU
System registers
Address logic
System buses
Scheduler
Branching of instructions
Interrupts
Bus synchronization
RAM memories
ROM memories
Flash memories
CAM memories
(V. MELINI)
Introduction to the IC Digital Design Phases
ASIC & FPGA Design flows and their differences
Static Time Analisys, how, why and when to use it
Analisys of the timing paths, and delays calculation
Definitions of the timing checks and delay calculations
Set-Up & Hold violations and methodologies to resolved them
Metastability
Introduction to the Clock Domains Crossing (CDC) and the main methodologies to deal with it
Introduction to the Reset Domain Crossing (RDC) and the main methodologies to avoid issue
Teaching Material (only for registered users)
