Last Updates:

  • 26-03-2017: Si comunica che la lezione di domani 27-03-2017 non si terrà.

Professor: Luca Di Nunzio

E-mail: This email address is being protected from spambots. You need JavaScript enabled to view it.

Tel.: +39 06 72597810

This lab course is focused on the HDL RTL design of digital circuits and their implementation on FPGAs (Field Programmable Gate Arrays ). The course provides the student with the ability to design and simulate digital systems on FPGA.


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Course Program:

  • FPGA Architecture
  • Zynq Architecture (frm 2016-2017)
  • VHDL  Syntax
  • Design of Digital System in VHDL
  • Writing Test-bench in VHDL
  • Vivado/ISE Design Suite
  • Verilog foundamentals
  • Introduction to System Verilog
  • MATLAB /Simulink  foundamentals

Teaching Material

https://www.dropbox.com/sh/z9nttycmxvyj5p5/AABODzy9iaim9XLscs_7Ty4Ca?dl=0


 

We would like to thank XILINX for the hardware and software donation. 

In the following some projects realized thanks to the XILINX University Program:

 

Flexible Channel Extractor For Wideband Systems Based On Polyphase Filter Bank

http://www.jatit.org/volumes/Vol95No16/12Vol95No16.pdf

 

A new electric encoder position estimator based on the Chinese Remainder Theorem for the CMG performance improvements

http://ieeexplore.ieee.org/document/8050780/