Last Updates:

  • 26-06-2017: Si comunica che domani, martedì 27/06/2017, si terrà un'esercitazione straordinaria alle ore 14.30 in aula B16.
  • 09-06-2017: Sono stati aggiunti nella sezione download alcuni testi di esami degli anni passati. La prima prova scritta si terrà mercoledì 5-07-2017 alle ore 9.30 in aula C6. La seconda prova scritta si terrà mercoledì 19-07-2017 alle ore 14 in aula C11. Le date delle prove orali verranno comunicate in seguito.

Professor: Marco Re

E-mail: This email address is being protected from spambots. You need JavaScript enabled to view it. 

Tel.: +39 06 72597370

Course Description

The course...

Book: Introduction to Digital Systems

Authors: Milos Ercegovac, Tomas Lang, Jaime H. Moreno

Course Program second part:

  • Specification of Combinational Systems: definitions and specification level, data representation and coding, binary specification of combinational systems.
  • Combinational Integrated Circuits - Characteristics and Capabilities: representation of binary variables, structure and operation of CMOS gates, propagation delays, voltage variations and noise margins, power dissipation and delay-power product, Buses and three-state drivers, circuit characterization of a CMOS-family.
  • Description and Analysis of Gate Networks: definition, description and characteristics, sets of gates.
  • Design of Combinational Systems - two-level gate networks: minimal two-level networks, Karnaugh maps, minimization of sum of products and product of sums, design of multiple-output two-level gate networks, two-level NAND-NAND and NOR-NOR networks, limitations of two-level networks, programmable modules: PLA and PLA.
  • Design of Combinational Systems - Multilevel Gates Networks: transformations, alternative implementations, networks with XOR and XNOR gates, networks with two-input multiplexers.
  • Specification of Sequential Systems: synchronous sequential systems, representation of the state transition and output functions, time behavior and finite state machines, finite memory sequential systems, controllers, equivalent sequential systems and minimization of the number of states, binary specification of sequential systems, specification of different types of sequential systems.
  • Sequential Networks: canonical form, high-level and binary implementations, gated latch and D flip-flop, timing characteristics, analysis of canonical sequential networks, design of canonical sequential networks, other flip-flop modules: SR, JK, T, analysis of networks with flip-flops, design using special state assignments.

Teaching Material (only for registerd users)

 Seconda parte (prof. Marco Re)  


We would like to thank XILINX for the hardware and software donation.