Hardware Architectures for Digital Signal Processing

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Electronics IoT and Embedded Systems (EIES) – 2nd part 6 of 12 CFU 13 Agosto 2020
Elettronica per le Telecomunicazioni (ETE) – 12 CFU 13 Agosto 2020
Progetto di Circuiti e Sistemi VLSI (PCSV) – 9 CFU 13 Agosto 2020
Sistemi Digitali per l’Elaborazione di Segnali ed Immagini (SDESI) – 6 CFU 13 Agosto 2020

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HARDWARE ARCHITECTURES FOR
DIGITAL SIGNAL PROCESSING LAB.

University of Rome Tor VergataDept. of Electronic EngineeringVia del Politecnico 1, 00133, Rome, ItalyBuilding “Ingegneria dell’Informazione”, 2nd floor

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University of Rome Tor Vergata
Engineering Macro-area
Dept. of Electronic Engineering
Course of Study in Electronic Engineering
Master of Sciences in Mechatronics Engineering

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