Laboratorio di Elettronica Digitale (LED) – 6 CFU

Last Updates:

Professor: Luca Di Nunzio

E-mail: di.nunzio@ing.uniroma2.it 

Tel.: +39 06 72597810

Course description

This lab course is focused on the HDL RTL design of digital circuits and their implementation on FPGAs (Field Programmable Gate Arrays ). The course provides the student with the ability to design and simulate digital systems on FPGA.

Book: …

Authors: …

Course Program:

  • FPGA Architecture
  • Zynq Architecture (from 2016-2017)
  • Introduction to VHDL 
  • Design of Digital System in VHDL
  • Writing Test-bench in VHDL
  • Vivado/Design Suite
  • Verilog foundamentals
  • Introduction to System Verilog
  • MATLAB /Simulink  foundamentals

Teaching Material

In the following some projects realized thanks to the XILINX University Program:

 

  • An Efficient Hardware Implementation of Reinforcement Learning: The Q-Learning Algorithm

           https://ieeexplore.ieee.org/document/8937555

 

  • Efficient FPGA implementation of high speed digital delay for wideband beamforming using parallel architectures

https://journal.portalgaruda.org/index.php/EEI/article/view/1483

  • AW-SOM, an Algorithm for High-speed Learning in Hardware Self-Organizing Maps

https://ieeexplore.ieee.org/document/8681156

  • An automatic AW-SOM VHDL IP-core generator

http://www.insightsociety.org/ojaseit/index.php/ijaseit/article/view/9035

  • FPGA implementation of hand-written number recognition based on CNN

http://www.insightsociety.org/ojaseit/index.php/ijaseit/article/view/6948

  • Efficient Ensemble Machine Learning implementation on FPGA using Partial Reconfiguration 

https://link.springer.com/chapter/10.1007/978-3-030-11973-7_29

  • Flexible Channel Extractor For Wideband Systems Based On Polyphase Filter Bank

http://www.jatit.org/volumes/Vol95No16/12Vol95No16.pdf

  • A new electric encoder position estimator based on the Chinese Remainder Theorem for the CMG performance improvements

http://ieeexplore.ieee.org/document/8050780/

  • FPGA implementation of a low-power QRS extractor

https://link.springer.com/chapter/10.1007/978-3-319-93082-4_2