Laboratorio di Elettronica Digitale (LED) – 6 CFU

Last Updates:

Professor: Luca Di Nunzio

E-mail: di.nunzio@ing.uniroma2.it 

Tel.: +39 06 72597810

Course description

This lab course is focused on the HDL RTL design of digital circuits and their implementation on FPGAs (Field Programmable Gate Arrays ). The course provides the student with the ability to design and simulate digital systems on FPGA.

Book: …

Authors: …

Course Program:

  • FPGA Architecture
  •  VHDL 
    • Design of Combinational Systems 
    • Design of Sequential Systems
    • Writing Test-bench 
    • Design of DSP architectures
  • Vivado/Design Suite
  • Introduction to System Verilog
  • MATLAB /Simulink  foundamentals
  • Introduction to Zynq Architecture

Teaching Material

In the following, some projects realized thanks to the XILINX University Program

 

Cardarilli, G.C., Di Nunzio, L., Fazzolari, R., Re, M., Spano, S.

AW-SOM, an algorithm for high-speed learning in hardware self-organizing maps(2020)

IEEE Transactions on Circuits and Systems II: Express Briefs, 67 (2), art. no. 8681156, pp. 380-384

https://ieeexplore.ieee.org/document/8681156

Cardarilli, G.C., Nunzio, L.D., Fazzolari, R., Panella, M., Re, M., Rosato, A., Spanò, S.

A Parallel Hardware Implementation for 2D Hierarchical Clustering Based on Fuzzy Logic(2020) IEEE Transactions on Circuits and Systems II: Express Briefs, art. no. 9234481,

https://ieeexplore.ieee.org/document/9234481

 

Cardarilli, G.C., Fazzolari, R., Matta, M., Panella, M., Rosato, A., Spano, S.

An Energy-Aware Hardware Implementation of 2D Hierarchical Clustering(2020) Proceedings

IEEE International Conference on Environment and Electrical Engineering and 2020 IEEE Industrial and Commercial Power Systems Europe, EEEIC art. no. 9160773, .

https://ieeexplore.ieee.org/document/9160773 

Spanò, S., Cardarilli, G.C., Di Nunzio, L., Fazzolari, R., Giardino, D., Matta, M., Nannarelli, A., Re, M.

An efficient hardware implementation of reinforcement learning: The q-learning algorithm

(2019) IEEE Access, 7, art. no. 8937555, pp. 186340-186351.


https://ieeexplore.ieee.org/document/8937555

Cardarilli, G.C., Di Nunzio, L., Fazzolari, R., Giardino, D., Matta, M., Re, M., Spanò, S., Simone, L.

Efficient FPGA implementation of high speed digital delay for wideband beamforming using parallel architectures

(2019) Bulletin of Electrical Engineering and Informatics, 8 (2), pp. 422-427.
https://journal.portalgaruda.org/index.php/EEI/article/view/1483

Giardino, D., Matta, M., Spanò, S. An automatic

AW-SOM VHDL IP-core generator (2019)

International Journal on Advanced Science, Engineering and Information Technology, 9 (4), pp. 1136-1141.


http://www.insightsociety.org/ojaseit/index.php/ijaseit/article/view/9035

Giardino, D., Matta, M., Silvestri, F., Spanò, S., Trobiani, V.

FPGA implementation of hand-written number recognition based on CNN

(2019) International Journal on Advanced Science, Engineering and Information Technology, 9 (1), pp. 167-171.
http://www.insightsociety.org/ojaseit/index.php/ijaseit/article/view/6948

Cardarilli, G.C., Di Nunzio, L., Fazzolari, R., Giardino, D., Matta, M., Re, M., Silvestri, F., Spanò, S.

Efficient ensemble machine learning implementation on FPGA using partial reconfiguration

(2019) Lecture Notes in Electrical Engineering, 550 (9783030119720), pp. 253-259.
https://link.springer.com/chapter/10.1007/978-3-030-11973-7_29

Silvestri, F., Acciarito, S., Cardarilli, G.C., Khanal, G.M., Di Nunzio, L., Fazzolari, R., Re, M.

FPGA implementation of a low-power QRS extractor

(2019) Lecture Notes in Electrical Engineering, 512, pp. 9-15.

https://link.springer.com/chapter/10.1007/978-3-319-93082-4_2

 

Cardarilli, G.C., Di Nunzio, L., Fazzolari, R., Re, M., Silvestri, F., Spanò, S.

Energy consumption saving in embedded microprocessors using hardware accelerators(2018)

Telkomnika (Telecommunication Computing Electronics and Control), 16 (3), pp. 1019-1026. http://journal.uad.ac.id/index.php/TELKOMNIKA/article/view/9387/4844

 

Cardarilli, G.C., Di Nunzio, L., Fazzolari, R., Gerardi, L., Re, M., Campolo, G., Cascone, D.

A new electric encoder position estimator based on the Chinese Remainder Theorem for the CMG performance improvements

(2017) Proceedings – IEEE International Symposium on Circuits and Systems, art. no. 8050780,


http://ieeexplore.ieee.org/document/8050780/

Cappello, S., Cardarilli, G.C., di Nunzio, L., Fazzolari, R., Re, M., Albicocco, P.

Flexible channel extractor for wideband systems based on polyphase filter bank

(2017) Journal of Theoretical and Applied Information Technology, 95 (16), pp. 3841-3850.
http://www.jatit.org/volumes/Vol95No16/12Vol95No16.pdf