Last Updates:
- 10-02-2020: The exam of 24-02-2020 will be held in the class room B3 (from 10.30 to 13.30) and C11 (from 14:00 to 18.00).
- 10-02-2020: Important info about next exam – The exam is divided in two parts: a first thirty-minutes written test composed of four exercises with multiple answers and then the oral exam. Only students who correctly solve all 4 exercises will be admitted to the oral exam. The oral test will take place immediately after the first written test. The class room of written test will be communicate asap.
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Professor: Marco Re E-mail: marco.re@uniroma2.it Tel.: +39 0672597370
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Tutor: Rocco Fazzolari E-mail: rocco.fazzolari@uniroma2.it Tel.: +39 0672597810 Reception Hours: Tuesday 15:00 |
Course Description
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Book: Introduction to Digital Systems
Authors: Milos Ercegovac, Tomas Lang, Jaime H. Moreno
Course Program first part:
- Specification of Combinational Systems: definitions and specification level, data representation and coding, binary specification of combinational systems.
- Combinational Integrated Circuits – Characteristics and Capabilities: representation of binary variables, structure and operation of CMOS gates, propagation delays, voltage variations and noise margins, power dissipation and delay-power product, Buses and three-state drivers, circuit characterization of a CMOS-family.
- Description and Analysis of Gate Networks: definition, description and characteristics, sets of gates.
- Design of Combinational Systems – two-level gate networks: minimal two-level networks, Karnaugh maps, minimization of sum of products and product of sums, design of multiple-output two-level gate networks, two-level NAND-NAND and NOR-NOR networks, limitations of two-level networks, programmable modules: PLA and PLA.
- Design of Combinational Systems – Multilevel Gates Networks: transformations, alternative implementations, networks with XOR and XNOR gates, networks with two-input multiplexers.
- Specification of Sequential Systems: synchronous sequential systems, representation of the state transition and output functions, time behavior and finite state machines, finite memory sequential systems, controllers, equivalent sequential systems and minimization of the number of states, binary specification of sequential systems, specification of different types of sequential systems.
- Sequential Networks: canonical form, high-level and binary implementations, gated latch and D flip-flop, timing characteristics, analysis of canonical sequential networks, design of canonical sequential networks, other flip-flop modules: SR, JK, T, analysis of networks with flip-flops, design using special state assignments.
Course Program second part:
- Standard Combinational Modules: Encoders/Decoders, Multiplexers/Demultiplexers, Shifters.
- Arithmetic Combinational Modules and Networks: Adders, Comparators, Multipliers.
- Standard Sequential Modules: Registers, Shift Registers, Counters, Multimodule Systems.
- Data and Control Subsystems: Data Subsystem, Control Subsystem, Microprogrammed Controller.
Teaching Material (only for registered users)
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