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Hardware Architectures for Digital Signal Processing

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Home
Team
Teaching
Research
- Activities
- Publications
Collaborations
About us
- Where we are
User Area
- Log In
- Register

Collaborations

Industrial Collaborations:

Thales Alenia Space Italia/France
Agenzia Spaziale Italiana (ASI)
Leonanrdo – Finmeccanica (ex Selex groups)
Elettronica SPA
INAIL

University Collaborations:

Technical University of Denmark (DTU)
University of Princeton
University of California at Berkeley
Technical University of Iasi

Latest Updates

Teaching

Elettronica Digitale (ED) – 12 CFU 14 Gennaio 2022
Fondamenti di Elettronica II parte (FdE) – 4.5 di 9 CFU 27 Maggio 2021
Elettronica per le Telecomunicazioni (ETE) – 12 CFU 24 Aprile 2021
Progetto di Circuiti e Sistemi VLSI (PCSV) – 9 CFU 24 Aprile 2021

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HARDWARE ARCHITECTURES FOR
DIGITAL SIGNAL PROCESSING LAB.

University of Rome Tor VergataDept. of Electronic EngineeringVia del Politecnico 1, 00133, Rome, ItalyBuilding “Ingegneria dell’Informazione”, 2nd floor

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University of Rome Tor Vergata
Engineering Macro-area
Dept. of Electronic Engineering
Course of Study in Electronic Engineering
Master of Sciences in Mechatronics Engineering

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