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Hardware Architectures for Digital Signal Processing

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Engineering Sciences

Digital Electronics (DE) – 9 CFU

YEAR 3 – SEMESTER 1
VLSI Circuits and Systems Design (VLSI) – 9 CFU

YEAR 3 – SEMESTER 2

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Teaching

Fondamenti di Elettronica II parte (FdE) – 4.5 di 9 CFU 27 Maggio 2021
Digital Electronics (DE) – 9 CFU 17 Maggio 2020
Architetture e Sistemi VLSI (ASVLSI) – 12 CFU 21 Marzo 2020

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HARDWARE ARCHITECTURES FOR
DIGITAL SIGNAL PROCESSING LAB.

University of Rome Tor VergataDept. of Electronic EngineeringVia del Politecnico 1, 00133, Rome, ItalyBuilding “Ingegneria dell’Informazione”, 2nd floor

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University of Rome Tor Vergata
Engineering Macro-area
Dept. of Electronic Engineering
Course of Study in Electronic Engineering
Master of Sciences in Mechatronics Engineering

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