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Hardware Architectures for Digital Signal Processing

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  • Home
  • Team
    • Professors
    • Researchers
    • PostDoc
    • PhD Students
  • Teaching
    • Exams Enrollment during COVID-19
    • CdS Ing. Elettronica
    • MS Mechatronics Eng.
    • Bach. Eng. Sciences
  • Research
    • Activities
    • Publications
  • Collaborations
  • About us
    • Where we are
  • User Area
    • Log In
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Teaching

  • Digital Electronics (DE) – 9 CFU

    YEAR 3 – SEMESTER 1

  • Electronics IoT and Embedded Systems (EIES) – 2nd part 6 of 12 CFU

    YEAR 2 – SEMESTER 1

  • VLSI Circuits and Systems Design (VLSI) – 9 CFU

    YEAR 3 – SEMESTER 2

  • Sistemi Digitali per l’Elaborazione di Segnali ed Immagini (SDESI) – 6 CFU

    ANNO 1 MAGISTRALE – SEMESTRE 1

  • Laboratorio di Elettronica Digitale (LED) – 6 CFU

    ANNO 3 – SEMESTRE 2

  • Fondamenti di Elettronica II parte (FdE) – 4.5 di 9 CFU

    ANNO 2 – SEMESTRE 2

  • Elettronica per le Telecomunicazioni (ETE) – 12 CFU

    ANNO 2 MAGISTRALE – SEMESTRE 1

  • Architetture e Sistemi VLSI (ASVLSI) – 12 CFU

    ANNO 2 MAGISTRALE – SEMESTRE 2

  • Elettronica Digitale (ED) – 12 CFU

    ANNO 3 – SEMESTRE 1

  • Progetto di Circuiti e Sistemi VLSI (PCSV) – 9 CFU

    ANNO 1 MAGISTRALE – SEMESTRE 2

Latest Updates

Teaching
  • Elettronica per le Telecomunicazioni (ETE) – 12 CFU 20 Giugno 2022
  • Progetto di Circuiti e Sistemi VLSI (PCSV) – 9 CFU 20 Giugno 2022
  • Sistemi Digitali per l’Elaborazione di Segnali ed Immagini (SDESI) – 6 CFU 20 Giugno 2022
  • Elettronica Digitale (ED) – 12 CFU 20 Giugno 2022
  • 1
  • 2
  • 3
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Info

HARDWARE ARCHITECTURES FOR
DIGITAL SIGNAL PROCESSING LAB.

University of Rome Tor Vergata
Dept. of Electronic Engineering
Via del Politecnico 1, 00133, Rome, Italy
Building “Ingegneria dell’Informazione”, 2nd floor

Useful Links

  • University of Rome Tor Vergata
  • Engineering Macro-area
  • Dept. of Electronic Engineering
  • Course of Study in Electronic Engineering
  • Master of Sciences in Mechatronics Engineering

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