The Hardware Architecture for Digital Signal Processing Lab. is located in the Department of Electronic Engineering of University of Rome Tor Vergata. It is active in the design of circuits and digital systems for many years. Activity was mainly focused on two topics, hardware architectures for Digital Signal Processing and fault-tolerant digital architectures.

About the first topic, different aspects have been investigated. In the past the group has been involved in the study of hardware structures for speech synthesis and compression. More recently, the design of processing hardware architectures for telecommunications and radar became the main topic of interest.

Due to the research group specific experience, the research efforts have been concentrated at the interface between the processing algorithms and their hardware implementation. In fact this is a critical part of the design phase due to the required skills.

The followed design flow includes the following steps:

  1. Algorithm acquisition (this step requires the study of the algorithm, the characterization of its basic properties and the classification of the different versions proposed in the literature).
  2. Application fitting (we take advantage of the peculiarities of the proposed algorithm to solve the problem).
  3. Implementation driven algorithm modifications and definition of specific implementation aspects (in this phase different operation flows are evaluated in terms of behaviour and complexity, moreover, particular attention is paid for the definition of the word length required in each processor node)
  4. Hardware implementation (the above process is validated through the physical design of the processing unit, the implementation is based either on a standard cells or a FPGA approach).

This methodology has been applied to different DSP applications such as, for example, speech compression systems based on speech synthesis techniques, digital filters, digital modulators and demodulators, and coding/decoding units -either for conventional codes, as Reed-Solomon block codes, or turbo codes.

These activities have been performed autonomously or cooperating with different industrial and research labs (for example, cooperations were actived with Merloni Elettrodomestici, Thales Alenia Space, Selex SI, Elettronica S.p.A., Project for Advanced Research of Architecture and Design of Electronic Systems (PARADES), STM, Siemens and Laben.).

The research on fault-tolerant architectures has been developed considering the use of electronic components in hostile environments (as that related to aerospace and automotive applications). The research goal has been the behavioural characterization of COTS (commercial off-the-shelf) components, when used in such environments. Moreover, suitable fault-tolerant architectures have been developed and evaluated in order to face the above effects.

The activity concerning digital architecture design has faced the problem of realizing self-checking, fail-safe and fault-tolerance processing systems. Concurrent Error Detection (CED) has been obtained by using different methodologies as, for example, those based on error detecting and correcting codes.

The research team has implemented different prototypes for the validation of the designed architectures.